Title: Electrostatic protection circuit in integrated circuit
Application Number: 200510111177 Application Date: 2005.12.06
Publication Number: 1979845 Publication Date: 2007.06.13
Approval Pub. Date: Granted Pub. Date:
International Classifi-cation: H01L23/60;H01L23/62;H01L27/02;H01L27/04;H05F3/04;H02H9/04
Applicant(s) Name: Huahong NEC Electronics Co., Ltd., Shanghai Address:
Inventor(s) Name: Xu Xiangming
Attorney & Agent: dingji tie
Abstract:
    The protection circuit includes hyperdactylia paralleled GGNMOS circuit, and diode. Drain pole of GGNMOS is connected to previous stage of internal circuit. Source pole of the middle GGNMOS and substrate are connected to cathode of the diode, and grid pole is connected to ground. Source poles and substrates of the other GGNMOS are connected to ground; grid poles connected to each other are connected to cathode of the diode. Anode of diode is connected to ground. When ESD occurs, the middle GGNMOS is turned to on first so as to generate bias voltage at diode, and provide the bias for grid pole of all peripheral GGNMOS. Thus, all GGNMOS in the protection circuit are turned to open uniformly. The invention is suitable for manufacturing IC.
Time: 8