Title: Apparatus and method for reducing solder pad size in an electrical lead suspension
Application Number: 200510136199 Application Date: 2005.12.20
Publication Number: 1838251 Publication Date: 2006.09.27
Approval Pub. Date: Granted Pub. Date:
International Classifi-cation: G11B5/48,G11B5/596,G11B21/10,H05K3/34
Applicant(s) Name: Hitachi Global Storage Tech Address:
Inventor(s) Name: Arya Satya P.
Attorney & Agent: li xiaoshu wei xiaogang
Abstract:
     An apparatus and method for reducing solder pad size in an electrical lead suspension (ELS) to decrease signal path capacitive discontinuities. The method provides a base-metal layer for the ELS. A dielectric layer above the base-metal layer is also provided. A signal conductive layer is provided above dielectric layer. The signal conductive layer carries at least one solder pad portion, wherein both a size of the solder pad portion and an amount of solder applied to the solder pad portion are reduced such that the solder pad to a ground, and solder on the solder pad to adjacent solder on adjacent pads, capacitance are reduced providing low signal reflection losses and a decrease in cross-talk.
Time: 13
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