Title: Data multi-way multiplying apparatus having single external memory
Application Number: 98120650 Application Date: 1998.09.22
Publication Number: 1234692 Publication Date: 1999.11.10
Approval Pub. Date: 2004.09.08 Granted Pub. Date: 2004.09.08
International Classifi-cation: H04J3/16;H04N7/52
Applicant(s) Name: Nippon Electric Co., Ltd. Address:
Inventor(s) Name: Hiayanao Nori
Attorney & Agent: wang zhongzhong
Abstract:
    In a data multiplexing apparatus, a single external memory stores different kinds of transfer data. A header cache memory stores the system header and the header data, and a plurality of data cache memories stores the transfer data. The cache memories are connected via an internal bus to the external memory. A data input circuit sequentially fetches the transfer data from the external memory on a time division basis, so that the transfer data is stored in one of the data cache memories. Also, a system clock signal generation circuit constantly generates a system clock signal indicating the current time. A selector circuit sequentially selects the cache memories and generates a system stream formed by the system header, the header data and the transfer data.
Time: 10