Title: Arithmetic circuit
Application Number: 200610169052 Application Date: 2006.12.20
Publication Number: 1988391 Publication Date: 2007.06.27
Approval Pub. Date: Granted Pub. Date:
International Classifi-cation: H03M13/00;H03M13/29;H03M13/11;H03M13/27;H04L1/00
Applicant(s) Name: NEC Electronics Corp. Address:
Inventor(s) Name: Orio Masao
Attorney & Agent: zhongqiang fanwei min
Abstract:
    An arithmetic circuit includes a NOR circuit for outputting 1-bit inverted logical OR sf from all of a first bit group x( 6 ) to x( 10 ) containing 0 or more high-order bit of a path metric value composed of a plurality of bits, an inverter for inverting each bit of a second bit group x( 2 ) to x( 5 ) and outputting a third bit group rs( 0 ) to rs( 3 ), an AND circuit for outputting a fourth bit group ns( 0 ) to ns( 3 ) that contain results of calculating a logical AND of sf and rs( 0 ) to rs( 3 ), and a CF output section for outputting a correction factor CF based on ns( 0 ) to ns( 3 ).
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