Title: Reed-solomon decoder key equation and error value solving-optimizing circuit
Application Number: 200610096837 Application Date: 2006.10.20
Publication Number: 1937412 Publication Date: 2007.03.28
Approval Pub. Date: Granted Pub. Date:
International Classifi-cation: H03M13/05;H03M13/09;H04L1/00
Applicant(s) Name: Dongnan Univ. Address:
Inventor(s) Name:
Attorney & Agent: luzhi bin
Abstract:
    To solve problems of the large size of circuit board and its high cost in the design of Leed Solomon decoder circuit using the traditional technique, this invention provides an optimum solving circuit of the key equation and error value of Leed Solomon decoder. The combination of selector, multiplier, adder, 3-way selector, giving original value and 3-state function circuit, flip-flop, latch, static memory, select and reciprocating circuit and select/flip-flop circuit realizes the solving error position polynomial (x), error value polynomial (x) and final error value. It utilizes reusing the single circuit to realize the function, which needs usually two circuits. Therefore, the circuit size, complicacy and the cost are as reduced as possible.
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