Title: Double-turbine structure low-density odd-even check code decoder
Application Number: 200610096535 Application Date: 2006.09.30
Publication Number: 1937413 Publication Date: 2007.03.28
Approval Pub. Date: Granted Pub. Date:
International Classifi-cation: H03M13/11;H03M13/19;H04L1/00
Applicant(s) Name: Dongnan Univ. Address:
Inventor(s) Name:
Attorney & Agent: yelian sheng
Abstract:
    It includes the verification node processing unit (VeNP) array, the variable node processing unit (VaNP) array, the verification node output info memory, the variable node output info memory, the original info memory, the convergence test unit, the iterative control unit, etc. According to the code verification matrix, the decoder splits the variable node and the verification node into blocks. All VANP and VeNP work simultaneously, interact info via memories and handle iterative decoding. Meanwhile, they optimize the original position of processing variable node blocks and verification node blocks, enlarge the proportion of using soft info in advance during the iterative decoding progress. This improves further the feature of the decoder. This synchronization parallel iterative decoder possesses feature of rapidly converging, good performance and durability and suits for various low density odd-even correcting code with sub-circular structure.
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