Title: Pipeline ADC with minimum overhead digital error correction
Application Number: 200610129196 Application Date: 2006.09.08
Publication Number: 1929312 Publication Date: 2007.03.14
Approval Pub. Date: Granted Pub. Date:
International Classifi-cation: H03M1/12
Applicant(s) Name: Realtek Semiconductor Corp. Address:
Inventor(s) Name:
Attorney & Agent: huangxiao lin wangzhi sen
Abstract:
    The most hardware efficient way to implement an N-stage pipeline ADC is to use (G 1)-level ADC-DAC for its first (N-1) stages and use (2.G-1)-level ADC for the last stage, where G is the inter-stage gain. For the fist (N-1) stages using (G 1)-level ADC-DAC, the (G 1) levels are uniformly distributed between -(G-1)/G and (G-1)/G; inclusively. The spacing between two adjacent levels is 2(G-1)/G
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