Title: Duty radio detecting circuit, dll circuit with the same and semiconductor device
Application Number: 200610143203 Application Date: 2006.10.30
Publication Number: 1955746 Publication Date: 2007.05.02
Approval Pub. Date: Granted Pub. Date:
International Classifi-cation: G01R29/00;G01R29/02;H03K5/156;H03L7/00;H03L7/08;G11C7/10;G11C7/22
Applicant(s) Name: Nihitatsu Memory Co., Ltd. Address:
Inventor(s) Name: Fujisawa Hiroki;Takishita Takaharu
Attorney & Agent: lujin hua liya
Abstract:
    Accurate duty detection is enabled by performing duty detection once every two cycles while delaying detection of one clock logic level by a half cycle, and presetting the potential of a common contact to an initial set value during the delay time. A DLL circuit employing a divide-by-two scheme is provided with separate duty detection circuits for even-numbered and odd-numbered cycles to detect duties of the respective cycles, respectively. The DLL circuit having this configuration and a semiconductor device having such DLL circuit are capable of accurate timing adjustment to the clock.
Time: 15
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