Title: Duty cycle correction circuit, clock pulse generation circuits, and related apparatus and method
Application Number: 200610142811 Application Date: 2006.10.26
Publication Number: 1956333 Publication Date: 2007.05.02
Approval Pub. Date: Granted Pub. Date:
International Classifi-cation: H03K5/156;H03L7/081;H03L7/07
Applicant(s) Name: Samsung Electronics Co., Ltd. Address:
Inventor(s) Name: Park Moon Sook;Kim Kyu Hyoun
Attorney & Agent: guoding hui huangxiao lin
Abstract:
    The invention provides a semiconductor device and method of generating clock signals where a phase lock loop (PLL), or a delay lock loop (DLL), comprises a duty cycle correction circuit (DCC) having a shared charge pump and a plurality of amplification parts. The plurality of amplification parts generate internal clock signals. The shared charge pump adjusts voltage level of control signal (VC) in response to the internal clock signals and provides the control signal VC to each of the amplification parts.
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