Title: Phase locked loop with temperature compensation
Application Number: 200610126948 Application Date: 2006.09.06
Publication Number: 1929308 Publication Date: 2007.03.14
Approval Pub. Date: Granted Pub. Date:
International Classifi-cation: H03L7/08;H03L7/099
Applicant(s) Name: Marvell World Trade Ltd. Address:
Inventor(s) Name:
Attorney & Agent: wangyi
Abstract:
    An integrated circuit (IC) package comprises an IC wafer and an annealed glass paste (AGP) layer that is arranged adjacent to the IC wafer. A molding material encapsulates at least part of the IC wafer and the AGP layer. The AGP layer is arranged on at least one side of the IC wafer. The AGP layer is arranged on a plurality of disjoint areas on at least one side of the IC wafer. A layer of a conductive material is arranged on a portion of the AGP layer.
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