Title: Delay cell of voltage controlled delay line using digital and analog control scheme
Application Number: 200610108799 Application Date: 2006.08.16
Publication Number: 1941184 Publication Date: 2007.04.04
Approval Pub. Date: Granted Pub. Date:
International Classifi-cation: G11C11/4076;G11C11/406;G11C7/22;H03L7/06
Applicant(s) Name: Hynix Semiconductor Inc. Address:
Inventor(s) Name:
Attorney & Agent: guoding hui huangxiao lin
Abstract:
    Provided is an analog/digital control delay locked loop (DLL). The DLL includes: a phase detector for detecting a phase difference between an input clock signal and a feedback signal to provide an up detection signal or a down detection signal; a charge pump for generating an adjusted output current based on the up or down signals; a loop filter for low pass-filtering the output current to produce an analog control voltage; a voltage controlled delay Line (VCDL) for receiving the analog control voltage, the input clock signal and a digital code, and delaying the input clock signal based on the analog control voltage and the digital code to provide an output clock signal; a delay replica modeling unit formed by replica of delay factors for producing the feedback signal depending on the output clock signal; and a digital code generator for generating the digital code.
Time: 16
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