Title: Delay locked loop circuit
Application Number: 200610108732 Application Date: 2006.08.10
Publication Number: 1941170 Publication Date: 2007.04.04
Approval Pub. Date: Granted Pub. Date:
International Classifi-cation: G11C7/22;G11C11/406;G11C11/4076;H03L7/08
Applicant(s) Name: Hynix Semiconductor Inc. Address:
Inventor(s) Name:
Attorney & Agent: lifang hua diwan kui
Abstract:
    A DLL of a memory device having a normal mode and a power down mode includes a clock buffer for buffering an external clock signal to output an internal clock signal. A power down mode controller generates a power down mode control signal to define the normal mode or the power down mode in response to a clock enable signal. A source clock generation unit receives the internal clock signal to generate a DLL source clock signal under the control of the power down mode control signal. A phase update unit performs a phase update operation based on the DLL source clock signal to output a DLL clock signal.
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