Title: Clock pulse generating circuit
Application Number: 200610109199 Application Date: 2006.08.09
Publication Number: 1913720 Publication Date: 2007.02.14
Approval Pub. Date: Granted Pub. Date:
International Classifi-cation: H04Q11/04;H03L7/08;G06F1/04;H04L7/00
Applicant(s) Name: Ricoh Co., Ltd. Address:
Inventor(s) Name: Sugiura Shingi;Matsushima Makoto
Attorney & Agent: yang wu wang jinggang
Abstract:
    The invention is to obtain a clock generation circuit having a PLL circuit and capable of evading the generation of abnormality at the switching of clocks independently of the signal levels of a current reference frequency dividing clock and a switched reference frequency dividing clock and the signal level of a comparing frequency dividing signal at the switching of clocks, and capable of sharply easing limitation in frequencies to be used for an input reference clock. Immediately after switching of input clocks CLK1, CLK2, first and second reference frequency dividing circuits 16, 17 and first and second comparing frequency dividing circuits 19, 20 are respectively reset, a pulse signal C is respectively added to a reference selection clock SEL1 outputted from a first selection circuit 15 and a comparison selection clock SEL2 outputted from a second selection circuit 18 and respective clocks SEL1, SEL2 to which the pulse signal C is respectively added are inputted to the PLL circuit 11.
Time: 13