Title: Wide range and dynamically reconfigurable clock data recovery architecture
Application Number: 200610126365 Application Date: 2006.08.02
Publication Number: 1909441 Publication Date: 2007.02.07
Approval Pub. Date: Granted Pub. Date:
International Classifi-cation: H04L5/26;H03L7/18
Applicant(s) Name: Altera Corp. Address:
Inventor(s) Name: Hoang Tim Tri;Shumarayev Sergey;Wong Wilson;Rakesh
Attorney & Agent: zhao rongmin
Abstract:
    Wide range and dynamically reprogrammable CDR architecture recovers an embedded clock signal from serial input data with a wide range of operating frequencies. In order to support a wide range of data rates, the CDR architecture includes multiple operating parameters. These parameters include various pre/post divider settings, charge pump currents, loop-filter and bandwidth selections, and VCO gears. The parameters may be dynamically reprogrammed without powering down the circuitry or PLD. This allows the CDR circuitry to switch between various standards and protocols on-the-fly.
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