Title: Phase locked loop fast lock method
Application Number: 200610103689 Application Date: 2006.07.28
Publication Number: 1913357 Publication Date: 2007.02.14
Approval Pub. Date: Granted Pub. Date:
International Classifi-cation: H03L7/08;H03L7/093;H03L7/18
Applicant(s) Name: Zarlink Semiconductor Inc. Address:
Inventor(s) Name: Spijker Menno T.;Rosinski Jason R. Jr.;Van Der Val
Attorney & Agent: sun haochen zhu shiding
Abstract:
    The present invention is a method to rapidly lock a type II phase locked loop (PLL) after a frequency jump without degrading the output signal much. The method to decrease the settling time and improve the quality of the output clock during the settling disclosed herein comprises of the following broad steps: Estimate new frequency offset with a separate circuit outside the PLL loop to measure the frequency of the input signal accurately. Ramp integrator to the new frequency offset. Do phase build out or phase pull-in. The remaining phase offset is build out when no edge to edge alignment is required. Otherwise, the remaining phase offset is pulled in while the integrator in the PLL
Time: 14