Title: Data differentiating circuit for clock data recovery circuit and its differentiating method
Application Number: 200610088318 Application Date: 2006.07.10
Publication Number: 1909423 Publication Date: 2007.02.07
Approval Pub. Date: Granted Pub. Date:
International Classifi-cation: H04B10/17;H04L7/033;H03L7/07
Applicant(s) Name: Southeast University Address:
Inventor(s) Name: Chen Yingmei;Wang Zhigong
Attorney & Agent: ye liansheng
Abstract:
    The invention relates to a data identify method of data identify circuit in clock data recover time, which can be used in the clock data recover circuit of fiber communication network and modern digit communication system, wherein said method uses the first exclusive-OR gate (21), the second exclusive-OR gate (22), the third exclusive-OR gate (23), the fourth exclusive-OR gate (24), the first 2:1 selector (25); the second 2:1 selector (26) to form advance lagging identify circuit (2), which uses the forward multi-phase sample circuit (i) to over sample to obtain six paths of input data as a, b, c1, c2, d, and e, as the data input ports of the first, second, third and fourth exclusive-OR gates; the clock (CK) is used as the clock input port of first and second selectors; the first 2;1 selector (25) outputs advance signal and the second 2:1 selector (26) outputs lagging signal.
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