Title: Multi-phase orthogonal clock generating circuit based on phase interpolation selection
Application Number: 200610043016 Application Date: 2006.06.23
Publication Number: 1897583 Publication Date: 2007.01.17
Approval Pub. Date: Granted Pub. Date:
International Classifi-cation: H04L25/03;H04L25/40;H04L7/04;H03L7/00
Applicant(s) Name: Xi Address:
Inventor(s) Name: Zeng Zecang;Jiang Lin;Liu Zhaoyuan;Deng Junyong;Hu
Attorney & Agent: peng dongyang
Abstract:
    The invention comprises: 8 phase interpolating and selecting circuits and one phase selecting circuit. The phase interpolating and selecting circuits divide the reference clock signals with the 16 phases and the pi/8 phase interval into 8 groups to make phase interpolation in order to generate the clock signals with 32 phases and pi/16 phase interval; by the control signals slc1_i,i=1,2,3,4, making phase selection to generate the clock signals with the 8 phases in two groups and the pi/2 inter group phase interval; wherein, clk1,3,5,7,clk2,4,6,8 are sequentially and effectively increased or decreased its phase according to the slc1_1,slc1_2,slc1_3, slc1_4, in a step length pi/16. under the control of the control signals slc2_j,j=1,2,L,6, the phase selecting circuit selects proper phase from the multiphase cross-clock signals; when slc2_5 is enabled, the phase of outputted clock signals clkI is between pi-2 pi, and is made the phase decreasing according to the slc2_1,slc2_2,slc2_3,slc2_4; when the step length is pi/4 and the slc2_6 is enabled, the phase of clkI is between 0-pi, the phase increasing is made for it according to slc2_1,slc2_2, slc2_3,slc2_4.
Time: 14