Title: Phase locked loop damping coefficient correction apparatus and method
Application Number: 200610091786 Application Date: 2006.06.12
Publication Number: 1881805 Publication Date: 2006.12.20
Approval Pub. Date: Granted Pub. Date:
International Classifi-cation: H03L7/08,H03L7/099,H03L7/18
Applicant(s) Name: VIA Tech Inc. Address:
Inventor(s) Name: Azam Mir S.
Attorney & Agent: bo maiwen huang xiaolin
Abstract:
     A damping coefficient correction mechanism for a PLL circuit including a gain controlled oscillator circuit, a damping controller, and gain compensation logic. The PLL circuit provides a loop control signal indicative of an error between first and second clock signals for generating a third clock signal having a frequency which is a clock multiplier times the frequency of the second clock signal. The oscillator has a control input receiving the loop control signal, a gain control input, and an output that provides the third clock signal. The damping controller has an input receiving the clock multiplier and an output providing a gain control signal to the gain control input of the oscillator. The damping controller adjusts gain of the oscillator in response to changes of the clock multiplier. The gain compensation logic is programmable and adjusts the gain control signal.
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