| Title: | Phase locked loop, signal generating apparatus and synchronization method | ||
| Application Number: | 200610081059 | Application Date: | 2006.05.23 |
| Publication Number: | 1870437 | Publication Date: | 2006.11.29 |
| Approval Pub. Date: | Granted Pub. Date: | ||
| International Classifi-cation: | H03L7/10,H03L7/18 | ||
| Applicant(s) Name: | Yokogawa Electric Corp. | Address: | |
| Inventor(s) Name: | |||
| Attorney & Agent: | chen yuan zhang tianshu | ||
|
|
|
||
Abstract: |
|||
| A phase locked loop for outputting a high frequency signal by executing synchronization and frequency conversion based on an input signal includes a control-type oscillator, and a phase comparator circuit for comparing a phase of the input signal and a phase of an output signal from the control-type oscillator, and outputting and supplying a phase error signal to the control-type oscillator via a loop filter. The phase locked loop further includes a correction signal generating circuit for adding a high frequency component of the phase error signal outputted from the phase comparator circuit to the phase error signal as a correction signal. In accordance with this phase locked loop, the high frequency component of the phase error signal outputted from the phase comparator circuit is added to an output signal of a loop filter as the correction signal so that a flat frequency characteristic can be acquired over a broad band. | |||
|
|
|||
| Time: | 14 | ||
<- Previous Patent:Frequency control device and info...
| Next Patent:Generation of low-frequency clock ->
|
|||