Title: Accelerating type n channel and p channel dynamic register
Application Number: 200610166993 Application Date: 2006.12.13
Publication Number: 1968018 Publication Date: 2007.05.23
Approval Pub. Date: Granted Pub. Date:
International Classifi-cation: H03K19/096
Applicant(s) Name: VIA Technologies, Inc. Address:
Inventor(s) Name: James R. Longboge;Roymond A. Baitelamu
Attorney & Agent: bomai wen huangxiao lin
Abstract:
    There is provided a noninverting dynamic register which comprises a domino stage, a multiplexer, and an output stage. The domino stage is used to estimate a logic function, on the basis of at least an input data signal and a pulse clock interrogate; when the pulse clock signal changes to high electric potential, an estimation window opens; a pre-charge node is set to low electric potential when an estimation is performed; if an estimation is not capable of being performed, the pre-charge node is hold on high electric potential. During the course of the estimation window, the multiplexer changes the feedback node to low electric potential when the pre-charge node changes to low electric potential; during the course of the estimation window, the feedback node is hold on high electric potential when the pre-charge node changes to low electric potential. The output stage is coupled to the pre-charge node and the feedback node and provides an output signal according to the states of the pre-charge node and the feedback node.
Time: 12