Title: Semiconductor integrated circuit and designing method thereof
Application Number: 200610162173 Application Date: 2006.12.07
Publication Number: 1987504 Publication Date: 2007.06.27
Approval Pub. Date: Granted Pub. Date:
International Classifi-cation: G01R31/3185;H03K19/173
Applicant(s) Name: Oki Electric Ind Co., Ltd. Address:
Inventor(s) Name: Baba Toshiaki
Attorney & Agent: luoyun po xuqian
Abstract:
    The present invention provides a semiconductor integrated circuit without particular considering the delay time in the scan path, and a design method. The structure of the semiconductor integrated circuit: latching a signal from the scan path (4) with the flip-latch (10), and providing a input terminal (SI) setting in the forestage scan FF (2) of the input terminal (1) in the logical block (1) for scaning the data. Combinating the corresponding flip-latch (10) and the scan FF (2), and activating the corresponding flip-latch (10) and the scan FF (2) in the different edge (if one side goes up, another side goes down) of the clock signal (CLK). In addition, setting a gate cell (12), which stop providing the clock signal (CLK) to the filp-latch (10) in commonly action.
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