Title: Retarding comparator circuit of single terminal input
Application Number: 200610124854 Application Date: 2006.10.25
Publication Number: 1949668 Publication Date: 2007.04.18
Approval Pub. Date: Granted Pub. Date:
International Classifi-cation: H03K5/24;G01R19/165
Applicant(s) Name: Huazhong Univ. of Science and Technology Address:
Inventor(s) Name: Zou Xuecheng;Liu Zhenglin;Zheng Zhaoxia;Zou Zhige;
Attorney & Agent: caobao jing
Abstract:
    The invention discloses a single-input hysteresis comparator circuit, comprising threshold voltage generating loop to generate threshold voltage and positive feedback branch to generate hysteresis voltage, where the positive feedback branch is composed of current source I3 and switch SW connected in series; the threshold voltage generating loop comprises PMOS tubes P1 and P2, NMOS tubes N3 and N4, and current sources I1 and I2; grid of the PMOS tube P1 is used as input end, drain of the PMOS tube P1 is earthed and source of the PMOS tube P1 is connected with source of the NMOS tube N3 and connected to the switch SW and the other end of the switch SW is connected with input end of the current source I3; grid and drain of the NMOS tube N3 are interconnected to grid of the NMOS tube N4 and output end of the current source I1; drain of the NMOS tube N4 is connected with output end of the current source I2, and source of the NMOS tube N4 is connected with that of the PMOS tube P2; grid and drain of the PMOS tube P2 are earthed; input ends of the current sources I1, I2 and I3 are all connected with power supply VDD. And it is designed to detect whether some voltage in a chip is overlow, and it has only one input end to input a voltage to be detected.
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