Title: P-domino register
Application Number: 200610136155 Application Date: 2006.10.13
Publication Number: 1929306 Publication Date: 2007.03.14
Approval Pub. Date: Granted Pub. Date:
International Classifi-cation: H03K19/094;H03K19/096
Applicant(s) Name: VIA Technology Inc. Address:
Inventor(s) Name:
Attorney & Agent: huangxiao lin wangzhi sen
Abstract:
    A P-domino register includes a domino stage, a write stage, an inverter, a low keeper path, a high keeper path, and an output stage. The domino stage is coupled to a pulsed clock signal, and evaluates a logic function according to the states of at least one data signal and the pulsed clock signal, where the domino stage pre-charges a pre-charged node low when the pulsed clock signal is high, and discharges the pre-charged node to a high state if the logic function evaluates when the pulsed clock signal is low, and keeps the pre-charged node low if the logic function fails to evaluate when the pulsed clock signal is low, where a setup state of the at least one data signal is provided to the domino stage when the pulsed clock signal is high.
Time: 8
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