Title: Area efficient fracturable logic elements
Application Number: 200610159804 Application Date: 2006.09.22
Publication Number: 1937409 Publication Date: 2007.03.28
Approval Pub. Date: Granted Pub. Date:
International Classifi-cation: H03K19/00
Applicant(s) Name: Altera Corp. Address:
Inventor(s) Name:
Attorney & Agent: huangze xiong tangshu hui
Abstract:
    A fracturable logic element includes a first, second, third, and fourth two-input lookup tables (2-LUTs). Each 2-LUT includes four memory elements. Each memory element is configured to hold one data bit. The fracturable logic element also includes a set of six inputs and a control circuit configured to operate in a first mode and a second mode. When the control circuit operates in the first mode, a first combinatorial output is generated using four of the set of six inputs and the first, second, third, and fourth 2-LUTs. When the control circuit operates in the second mode, a second combinatorial output is generated using a first subset of three of the set of six inputs and the first and second 2-LUTS. Additionally, when the control circuit operates in the second mode, a third combinatorial output is generated using a second subset of three of the set of six inputs and the third and fourth 2-LUTs, the first and second subsets being non-intersecting subsets of the set of six inputs.
Time: 9
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