Title: Delay cell and delay line circuit having the same
Application Number: 200610154322 Application Date: 2006.09.20
Publication Number: 1983811 Publication Date: 2007.06.20
Approval Pub. Date: Granted Pub. Date:
International Classifi-cation: H03K5/14
Applicant(s) Name: Samsung Electronics Co., Ltd. Address:
Inventor(s) Name: Chae Kwan Yeob
Attorney & Agent: wangzhi sen huangxiao lin
Abstract:
    Delay line circuits include a plurality of delay cells connected in series. The delay cells respectively include a first to a third logic gate. The first logic gate, in response to a selection signal, generates a first signal based on an input signal. The second logic gate generates a second signal based on the input signal in response to the selection signal. The third logic gate generates a third signal based on either a return signal or an output signal of the second logic gate.
Time: 9
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