Title: Programmable logic device architecture for accommodating specialized circuitry
Application Number: 200610154266 Application Date: 2006.09.19
Publication Number: 1937408 Publication Date: 2007.03.28
Approval Pub. Date: Granted Pub. Date:
International Classifi-cation: H03K19/00;H03K19/173
Applicant(s) Name: Altera Corp. Address:
Inventor(s) Name:
Attorney & Agent: zhaorong min
Abstract:
    A programmable logic device (PLD) having one or more programmable logic regions and one or more conventional input/output regions additionally has one or more peripheral areas including specialized circuitry. The peripheral specialized regions, which are not connected to the remainder of the programmable logic device (and may be made on separate dies from the remainder of the programmable logic device mounted on a common substrate), and one or both of the programmable logic regions and the conventional I/O regions, have contacts for metallization traces or other interconnections to connect the peripheral specialized regions to the remainder of the programmable logic device. The same PLD can be sold with or without the specialized circuitry capability by providing or not providing the interconnections. The peripheral specialized regions may include high-speed I/O (basic, up to about 3 Gbps, and enhanced, up to about 10-12 Gbps), as well as other types of specialized circuitry.
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