Title: Impedance adjusting circuit and method
Application Number: 200610105793 Application Date: 2006.07.25
Publication Number: 1905065 Publication Date: 2007.01.31
Approval Pub. Date: Granted Pub. Date:
International Classifi-cation: G11C11/417;H01L27/04;H03H11/28;G11C7/10
Applicant(s) Name: NEC Electronics Corp. Address:
Inventor(s) Name: Kuroki Koichi
Attorney & Agent: lu jinhua xie lina
Abstract:
    To adjust the impedance of an output buffer in a DDR2 memory through the use of an OCD impedance adjusting function from the side of a memory controller. An impedance adjusting circuit comprises first output buffers (P1, N1) for pull-up and pull-down and second buffers (P2, N2), which commonly receive an input signal with the freely variable impedance; first and second terminals (DQS, DQSB) for respectively receiving first and second signals to be output from the first and second buffers; first and second switches (SW1, SW2) serially connected between the first and second terminals; a comparator 12 for comparing a voltage at a connection point D1 between the first and second switches with a reference voltage VREF; and a control circuit 11 for receiving a comparison result from the comparator, performing control to variably set the impedance of the first and/or second buffers, and controlling the on/off of the first and second switches (SW1, SW2).
Time: 9
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