Title: Circuit for restraining LO leakage
Application Number: 200510024964 Application Date: 2005.04.07
Publication Number: 1845464 Publication Date: 2006.10.11
Approval Pub. Date: Granted Pub. Date:
International Classifi-cation: H04B1/04,H03D7/18
Applicant(s) Name: Shanghai Huawei Technologies Co., Ltd. Address: 200121
Inventor(s) Name:
Attorney & Agent: du yun
Abstract:
     The related circuit to suppress intrinsic leakage comprises: coupling the intrinsic output signal in the second branch as kill channel, delaying, regulating on amplitude and phase to let signal from kill channel with same amplitude and opposite phase to the one from mixer; then, superposing signals; besides, if failing to index requirement, adding the third branch composed by the third/fourth directional coupler and a second vector modulator for further suppression. This invention has reliable performance with small size and low cost.
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