| Title: | PLL circuit | ||
| Application Number: | 200580006038 | Application Date: | 2005.02.14 |
| Publication Number: | 1922787 | Publication Date: | 2007.02.28 |
| Approval Pub. Date: | Granted Pub. Date: | ||
| International Classifi-cation: | H03L7/18;H03L7/093;G06F1/04;H03C3/00 | ||
| Applicant(s) Name: | Sanyo Electric Co. | Address: | |
| Inventor(s) Name: | Kimura Syuji;Hashizume Takashi | ||
| Attorney & Agent: | li chunhui | ||
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Abstract: |
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| [PROBLEMS] To reduce EMI noise by use of a simple arrangement. [MEANS FOR SOLVING PROBLEMS] A PLL circuit comprising a control part for switching, at predetermined timings, the validity/invalidity of a phase difference signal to be supplied from a phase comparator to a lowpass filter; and a resistor element provided between a predetermined potential and a signal line used for supplying the phase difference signal from the phase comparator to the lowpass filter; wherein in the case of making the phase difference signal valid, an oscillator circuit is caused to oscillate based on a voltage signal responsive to the phase difference signal, and wherein in the case of making the phase difference signal invalid, the predetermined potential is supplied to the lowpass filter via the resistor element, and the oscillator circuit is caused to oscillate based on the voltage signal as produced in response to the supplied predetermined potential. | |||
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| Time: | 13 | ||
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