Title: Matrix switch
Application Number: 200680000170 Application Date: 2006.03.07
Publication Number: 1943074 Publication Date: 2007.04.04
Approval Pub. Date: Granted Pub. Date:
International Classifi-cation: H01P1/15;H01L27/095;H03K17/00
Applicant(s) Name: Nippon Telegraph Address:
Inventor(s) Name:
Attorney & Agent: wangwei
Abstract:
    Four SP4T switches (31 to 34) are grouped into two pairs so as to constitute two switch pairs. Four first conductor wires (411 to 414, 421 to 424) are respectively arranged between the SP4T switches (31 and 34, 32 and 33) constituting the switch pairs. Four second conductor wires (51 to 54) are connected to each one of the wires arranged in each of the switch pairs among the first conductor wires. The first and the second conductor wires are arranged on a dielectric layer having a lower surface on which a grounding conductor (6) is formed. The dielectric layer has a 2-layer configuration. The first conductor wires a re arranged on the first dielectric layer as a lower layer while the second conductor wires are arranged on the second dielectric layer as an upper layer. With this configuration, it is possible to reduce the size of the matrix, reduce the loss, and enable a wide-band operation.
Time: 8