Title: DRAM cell arrangement and method for producing the same
Application Number: 00804949 Application Date: 2000.03.10
Publication Number: 1343371 Publication Date: 2002.04.03
Approval Pub. Date: 2004.05.19 Granted Pub. Date: 2004.05.19
International Classifi-cation: H01L21/8242;H01L27/108
Applicant(s) Name: Infineon Technologies AG. Address:
Inventor(s) Name: J. Willer;B. Sell;T. Schleser
Attorney & Agent: ma tieliang
Abstract:
    Bit lines are arranged in the lower parts of trenches of a substrate. Word lines are located above the substrate except for protuberances or bulges, which extend downwards into the trenches and which are arranged above the bit lines. The transistors are vertical transistors whose source/drain regions are located below the word lines and between adjacent trenches. The capacitors are linked with the upper source/drain regions. Conductive structures that surround the word lines from the top and the sides while being insulated from the word lines and bordering on the upper source/drain regions can link the upper source/drain regions with the capacitors.
Time: 5