Title: Boost clock generation circuit and semiconductor device
Application Number: 200410059408 Application Date: 2004.06.18
Publication Number: 1574351 Publication Date: 2005.02.02
Approval Pub. Date: Granted Pub. Date:
International Classifi-cation: G02F1/133,G09G3/36,H01L27/00
Applicant(s) Name: Seiko Epson Corp. Address:
Inventor(s) Name:
Attorney & Agent: yu gang
Abstract:
     A boost clock generation circuit (500) including: a first switch circuit （502） connected between a first power supply line and a first clock output line to which the first boost clock signal is output; a second switch circuit (504) connected between a second power supply line and the first clock output line; a third switch circuit (506) connected between a third power supply line and a second clock output line to which the second boost clock signal is output; and a fourth switch circuit (508) connected between a fourth power supply line and the second clock output line. One of the first and second switch circuits is exclusively turned ON, and one of the third and fourth switch circuits is exclusively turned ON. The level of current drive capability of the first switch circuit differs from the level of current drive capability of the third switch circuit; and the level of current drive capability of the second switch circuit differs from the level of current drive capability of the fourth switch circuit.
Time: 9
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