Title: Display control circuit
Application Number: 200410061644 Application Date: 2004.06.24
Publication Number: 1573902 Publication Date: 2005.02.02
Approval Pub. Date: Granted Pub. Date:
International Classifi-cation: G09G3/20,G09G3/36
Applicant(s) Name: NEC Electronics Corp. Address:
Inventor(s) Name:
Attorney & Agent: mu dejun guan zhaohui
Abstract:
     Provided is a display control circuit that minimizes an offset voltage in a full range and prevents the DC gain of an input means in an input range from varying. The disclosed display control circuit is equipped with a selector circuit 1 which is connected to a digital image data signal line 100 and outputs an analog signal of level corresponding to inputted digital image data, an operational amplifier control circuit 3 which is connected to the digital image data signal line and outputs control signals 17 and 18 having a polarity corresponding to the inputted digital image data, and an operational amplifier 4 which has 1st input means M1 and M2 and 2nd input means M3 and M4 composed of complementarily connected differential transistor couples of mutually opposite conductivity types and is controlled to selectively turn on a 1st constant current source I1 supplying a bias current to the input means and a 2nd constant current source 12 supplying a bias current to the 2nd input stage according to the polarity of a control signal.
Time: 7