| Title: | Display | ||
| Application Number: | 200410059493 | Application Date: | 2004.06.28 |
| Publication Number: | 1577425 | Publication Date: | 2005.02.09 |
| Approval Pub. Date: | Granted Pub. Date: | ||
| International Classifi-cation: | G09G3/20 | ||
| Applicant(s) Name: | Sanyo Electric Co. | Address: | |
| Inventor(s) Name: | Uesugi Kenya | ||
| Attorney & Agent: | ge bo cheng wei | ||
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Abstract: |
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| Provided is a display device that can prevent image degradation. The display device comprises a shift register circuit 4a1 including an output side circuit part 4c1 having a p-channel transistor PT 1 that is connected to a negative potential HVSS side and turned on in response to a clock signal HCLK 1, a p-channel transistor PT 2 that is connected to a positive potential HVDD side, a p-channel transistor PT 3 that is connected between the gate of the p-channel transistor PT 1 and the positive potential HVDD side, and a high resistance R1 of about 100 k[Omega] connected between the gate of the p-channel transistor PT 1 and a clock signal line for supplying the clock signal HCLK 1. | |||
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| Time: | 6 | ||
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