Title: Display device
Application Number: 200410059491 Application Date: 2004.06.28
Publication Number: 1577021 Publication Date: 2005.02.09
Approval Pub. Date: 2007.04.25 Granted Pub. Date: 2007.04.25
International Classifi-cation: G02F1/136;G02F1/133;G09G3/36
Applicant(s) Name: Sanyo Electric Co., Ltd. Address:
Inventor(s) Name: Sano Kagekazu
Attorney & Agent: cheng wei wang jinyang
Abstract:
    Provided is a display device for suppressing an increase of a consumption current. The display device comprises: a p channel transistor PT1 connected to a negative side potential HVSS side; a p channel transistor PT2 connected to a positive side potential HVDD side; a p channel transistor PT3 connected between the gate of the p channel transistor PT1 and the positive side potential HVDD; a p channel transistor PT4 connected to the gate of the p channel transistor PT1 and turned on by responding to a clock signal HCLK1; and a shift register circuit 4a1 connected between first circuit sections 4b1, the p channel transistor PT4 and the negative side potential HVSS, turned on by responding to a clock signal HCLK2 being a reverse clock signal of the clock signal HCLK1 and having a p channel transistor PT5.
Time: 10
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