Title: Topological process of wiring diagram, semiconductor device and optical patter-correcting method
Application Number: 02118396 Application Date: 2002.04.26
Publication Number: 1384540 Publication Date: 2002.12.11
Approval Pub. Date: 2006.08.09 Granted Pub. Date: 2006.08.09
International Classifi-cation: H01L21/82;H01L23/535;G06F17/50
Applicant(s) Name: Toshiba K.K. Address:
Inventor(s) Name: Igarashi Mutsunori;Yamada Masaaki;Hashimoto Koji
Attorney & Agent: wang yonggang
Abstract:
    An automated wiring pattern layout method is provided. With this method, a first wiring pattern is generated with width W and extending in a first direction, and a second wiring pattern is generated with width W and extending in a direction perpendicular to the first wiring pattern in a manner such that the end thereof ends at the end portion of the first wiring pattern. Moreover, an overlapping region is generated by bending an end of either one of the first or the second wiring pattern at a right angle to produce an L-shaped extension and overlaying the first and the second wiring pattern, and a rectangular-shaped VIA pattern is generated at the overlapping region.
Time: 4
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