Title: Method and apparatus for performing operative testing on integrated circuit
Application Number: 98103705 Application Date: 1998.01.26
Publication Number: 1190255 Publication Date: 1998.08.12
Approval Pub. Date: Granted Pub. Date:
International Classifi-cation: G01R31/28;H01L21/66
Applicant(s) Name: Motorola, Inc. Address:
Inventor(s) Name: Bernard J. Pappert;Clark Shepard;Alfred Larry Crou
Attorney & Agent: fu jianjun
Abstract:
    A method of detecting defective CMOS devices by quiescent current (IDDQ) behavior using a monitor circuit resident in the expendable areas of a die and/or wafer. A monitor unit is incorporated into the scribe grid of a wafer, where pads are built in the corners of the die and connected to the monitor unit via metal connects in the wafer. The monitor unit (10) determines defective die based on IDDQ as expressed by decay of voltage (Vdd) in time, where Vdd is supplied to a die by way of a switch in the monitor unit. Alternate embodiments incorporate various configurations and incorporate functional and other tests into a wafer level test system.
Time: 24