Title: Circuit and test method
Application Number: 98103882 Application Date: 1998.02.17
Publication Number: 1191316 Publication Date: 1998.08.26
Approval Pub. Date: Granted Pub. Date:
International Classifi-cation: G01R31/28
Applicant(s) Name: Motorola, Inc. Address:
Inventor(s) Name: Udi Barel;Boaz Shahar;Ido Reuveny
Attorney & Agent: fu jianjun
Abstract:
    A circuit (100) comprises a built-in test circuit (150) which verifies the proper operation of input cells (130) when they receive signals at a first level (71) and at a second level (72). The test circuit (160) comprises a first and a second logic (110, 120) which receive power only when a test is performed. Thereby power consumption of the test circuit (160) is reduced. The first and the second logic (110, 120) are conveniently formed by a combination of parallel coupled transistors acting in an logical
Time: 31
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